Each test is 5 questions with varying difficulty.
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CUDA (Compute Unified Device Architecture) programming is the industry standard for general-purpose computing on NVIDIA GPUs. In 2026, as high-performance AI inference and large-scale data processing rely heavily on GPU acceleration, proficiency in CUDA is a critical skill for ML Engineers, Systems Engineers, and AI Infrastructure specialists. Interviewers focus on CUDA to assess a candidate's ability to reason about massive parallelism, hardware-level memory constraints, and the divergence between host (CPU) and device (GPU) execution models. For junior roles, the expectation is a solid grasp of kernel launches, thread indexing, and basic memory transfers. Senior candidates are expected to demonstrate deep knowledge of warp-level primitives, shared memory bank conflict mitigation, and occupancy optimization to maximize GPU throughput.
CUDA is the foundational layer for modern AI acceleration. With the shift toward disaggregated prefill-decode serving and custom kernels for LLM operations, the ability to write performant CUDA code directly impacts inference latency and hardware utilization. Companies like NVIDIA, OpenAI, and major cloud providers prioritize candidates who understand how to minimize host-to-device data movement and maximize compute density. A strong interview answer reveals a candidate's understanding of the GPU's SIMT (Single Instruction, Multiple Threads) architecture. Weak answers often treat the GPU like a CPU, failing to account for warp divergence or memory coalescing, which leads to massive performance degradation in production. In 2026, as model architectures evolve to require more custom operations, the ability to write efficient, low-level CUDA kernels is a high-signal indicator of an engineer's capability to build scalable AI infrastructure.
The CUDA architecture follows a SIMT execution model where the CPU (Host) manages the GPU (Device). The execution pipeline involves data transfer from host to device memory, kernel invocation, and result retrieval. Internally, the GPU schedules warps (groups of 32 threads) onto Streaming Multiprocessors (SMs).
[Host CPU]
↓
[CUDA Runtime API]
↓
[Global Memory (HBM)]
↓
[Streaming Multiprocessor]
↓
[Warp Scheduler]
↓
[Execution Units]
↓
[Register File/Shared Memory]Load data into __shared__ memory in blocks to reuse values across threads.
Trade-offs: Reduces global memory traffic but increases register pressure and shared memory usage.
Use __shfl_sync() for fast inter-thread communication within a warp without shared memory.
Trade-offs: Extremely fast but restricted to threads within the same warp.
Threads iterate over data with a stride equal to the total grid size to handle arbitrary input lengths.
Trade-offs: Ensures kernel robustness regardless of grid dimensions.
| Reliability | Use cudaDeviceSynchronize() and error checking macros for every API call to catch asynchronous errors. |
| Scalability | Use grid-stride loops to ensure kernels scale across different GPU architectures and input sizes. |
| Performance | Focus on memory bandwidth utilization; use Nsight Compute to identify memory vs compute bound kernels. |
| Cost | Minimize host-to-device transfers to reduce PCIe bus contention and latency. |
| Security | Validate input sizes and pointers to prevent out-of-bounds access that could crash the GPU driver. |
| Monitoring | Track kernel execution time and occupancy metrics via Nsight Systems. |
A block is a programmer-defined group of threads that can share memory and synchronize. A warp is the hardware-level unit of execution consisting of 32 threads. The GPU scheduler manages warps, not blocks directly.
Global memory access is high-latency. Coalescing allows the GPU to combine multiple thread requests into a single transaction, significantly reducing the number of memory requests and improving effective bandwidth.
Shared memory is an on-chip, user-managed cache within a thread block, offering very low latency and high bandwidth. Global memory is off-chip, high-capacity, and high-latency, accessible by all threads.
Warp divergence occurs when threads within a single warp follow different execution paths due to conditional branching (e.g., if-else). The hardware serializes these paths, reducing throughput.
Yes, but you must distinguish between host pointers and device pointers. You cannot dereference a device pointer on the host or vice versa without explicit memory transfers or unified memory.
The SM is the core execution unit of the GPU. It contains registers, shared memory, and execution units. It handles warp scheduling and resource allocation for threads.
No. CUDA is a proprietary platform by NVIDIA, while OpenCL is an open standard. CUDA is generally more mature and offers deeper integration with NVIDIA hardware features.
Focus on memory coalescing, using shared memory to reduce global traffic, and ensuring data structures are properly aligned for the memory controller.
Occupancy is the ratio of active warps on an SM to the maximum number of warps the SM can support. Higher occupancy helps the GPU hide memory latency.
Streams are sequences of operations that execute in order on the GPU. Multiple streams can run concurrently, allowing for overlapping data transfers with kernel execution.
AI Prep covers AI Agents, Generative AI, ML Fundamentals, NLP & LLMs and a lot more, with adaptive tests and daily challenges. Fully offline on Android. Free to try, one-time unlock for lifetime access.